	
	module gtp_tx(
	
		input	wire			clk 				,		
		input 	wire 			rst 				,	

        //测试数据发送接口		
		output 	wire [0 : 31] 	s_axi_tx_tdata		,
		output 	wire [0 : 3] 	s_axi_tx_tkeep		,
		output 	wire 			s_axi_tx_tlast		,
		output 	wire 			s_axi_tx_tvalid		,
		input 	wire 			s_axi_tx_tready		,

        //用户流控接口
		output 	wire 			s_axi_ufc_tx_tvalid	,	
		output 	wire [0 : 2] 	s_axi_ufc_tx_tdata	,
		input 	wire 			s_axi_ufc_tx_tready		
		
		);

	//==========================================
	//parameter defien
	//==========================================
	parameter 	STREAM_LEN = 8192 	;


	reg 	[0:31]	axi_tx_tdata			;
	reg 			axi_tx_tlast			;
	reg 			axi_tx_tvalid			;
	reg 			axi_ufc_tx_tvalid		;

	reg 	[15:0]	cnt_burst 				;
	wire 			add_cnt_burst 			;
	wire 			end_cnt_burst 			;

	assign s_axi_tx_tdata = axi_tx_tdata;
	assign s_axi_tx_tkeep = 4'hF;
	assign s_axi_tx_tlast = axi_tx_tlast;
	assign s_axi_tx_tvalid = axi_tx_tvalid;
	
	assign s_axi_ufc_tx_tvalid = axi_ufc_tx_tvalid;
	assign s_axi_ufc_tx_tdata = 3'b011;

	//----------------cnt_burst ------------------
	always @(posedge clk) begin
		if (rst == 1'b1) begin
			cnt_burst <= 'd0;
		end
		else if (add_cnt_burst) begin
			if(end_cnt_burst)
				cnt_burst <= 'd0;
			else
				cnt_burst <= cnt_burst + 1'b1;
		end
	end

	assign add_cnt_burst = s_axi_tx_tready & axi_tx_tvalid;
	assign end_cnt_burst = add_cnt_burst &&	cnt_burst == STREAM_LEN - 1;

	//-----------------axi_tx_tlast-----------------
	always @(*) begin
		axi_tx_tlast = end_cnt_burst;
	end

	//----------------axi_tx_tvalid------------------
	always @(posedge clk) begin
		if (rst==1'b1) begin
			axi_tx_tvalid <= 1'b0;
		end
		else if (end_cnt_burst == 1'b1) begin
			axi_tx_tvalid <= 1'b0;
		end
		else if (axi_tx_tvalid == 1'b0 && s_axi_tx_tready == 1'b1) begin
			axi_tx_tvalid <= 1'b1;
		end
	end

	//----------------axi_tx_tdata------------------
	always @(*) begin
		axi_tx_tdata = cnt_burst;
	end

	//----------------axi_ufc_tx_tvalid------------------
	
	//这里选择不添加用户流控机制
	always @(posedge clk) begin
		if (rst==1'b1) 
			begin
				axi_ufc_tx_tvalid <= 1'b0;
			end
		// else if (end_cnt_burst == 1'b1) 
			// begin
				// axi_ufc_tx_tvalid <= 1'b1;
			// end
		// else if (axi_ufc_tx_tvalid == 1'b1 && s_axi_ufc_tx_tready == 1'b1)
			// begin
				// axi_ufc_tx_tvalid <= 1'b0;
			// end
	end
	
	
	
	
	
	/* wire [127:0]	probe0;
	assign probe0 = {
		s_axi_tx_tdata		,
		s_axi_tx_tkeep		,
		s_axi_tx_tlast		,
		s_axi_tx_tvalid		,
		s_axi_tx_tready		,
		s_axi_ufc_tx_tvalid	,
		s_axi_ufc_tx_tdata	,
		s_axi_ufc_tx_tready	,
		cnt_burst

	};
	ila_0 inst_tx (
		.clk(clk), // input wire clk


		.probe0(probe0) // input wire [127:0] probe0
	);
	 */
	
	endmodule